1. Field of the Invention
This invention relates to the field of integrated circuits. More particularly, this invention relates to data and clock signal voltages within an integrated circuit.
2. Description of the Prior Art
It is known to provide integrated circuits which incorporate data processing circuitry configured to process data signals passing along a data path and using clock circuitry coupled to the data processing circuitry to regulate passage of the data signal along the data path under control of the clock signal. Such integrated circuits can take many different forms. Data values are typically passed along the data paths between data storage circuits which capture and store data values in synchronism with a clock signal. The clock signal provides timing control to the data processing circuitry and regulates the flow of data signals within the data processing circuitry.
In order to increase circuit density and reduce energy consumption there has been a drive towards forming integrated circuits using smaller process geometries to increase circuitry density and reduce energy consumption. However, as the geometries become smaller there is an increase in the level of variation in circuit performance that arises due to PVT variations (process, voltage, temperature). With a rise in the amount of variation in operating speed of the circuit elements which can arise it has become necessary to add increased levels of margin to the operational timing of the circuit so as to ensure that variations in the timing which occur as a consequence of PVT variations do not cause timing violations.
As an example, the input to a data signal capture and storage circuit (latch) may have a specified hold time which is a minimum time for which a data value to be captured and stored will be held at the input to that latch. If this hold time is too low, then it can produce a timing violation whereby a data signal from a following clock cycle is incorrectly captured in the preceding clock signal due to variations in the speed of operation of adjacent stages along the data path. One way of dealing with this problem is to provide hold buffers in the data path which serve to slow down data signal propagation in a manner that will ensure a sufficient hold time. However, the provision of such hold buffers increases the circuit area and energy overhead in a manner that reduces the benefits that can be achieved by moving to smaller process geometries and lower operating voltages.